Job Description

Design-for-Test Engineer

Acceler8 Talent is looking for an experienced Design-for-Test (DFT) Engineer to join a high-performing San Francisco-based team, helping them create best-in-class silicon for high-performance and sustainable Generative AI. If you’re looking to make an impact in this exciting age of technological advancement, this opportunity may be for you!

Founded by engineers who have been instrumental in the industry’s most successful semiconductor and AI products, this company is pushing the boundaries for what LLMs can accomplish. With a team comprised of industry veterans, talent and passion are the foundational pillars behind their success.

As a Silicon DFT Engineer, you would execute the company's DFT implementation/verification and collaborate on physical design methodology from RTL to GDS. You would integrate DFT interfaces from IP blocks, develop pattern porting flow, and identify and execute efficient and effective DFT solutions based on chip architecture.

This role might be ideal for you if you have:

• Experience with DFT implementation (MBIST and At-speed Scan) and executing on large and complex ASICs and SOCs to produce silicon
• Worked with the latest DFT technologies (IJTAG, Streaming Scan, etc.)
• Automated DFT flow / worked with Tessent DFT & Fusion Complier
• Familiarity with the integration of PHY DFT interfaces
• 5+ years of industry experience

This is a hybrid role based in Mountain View, CA.

Base Salary: $200,000 - $300,000 + equity + benefits

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