Physical Design Engineer Job at Technical-Link N. America, San Jose, CA

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  • Technical-Link N. America
  • San Jose, CA

Job Description

Physical Design / Place and Route Engineer

Responsibilities

  • Cadence - Innovus PNR flow expertise.
  • Experience with importing design in the Virtuoso environment.
  • Experience with physical design verification using stand alone Caliber.
  • Experience with putting a chiptop for a TO.
  • Experience with bump map creation.
  • Familiar with LEF/DEF generation for chip level as well as block level.
  • Familiar with TSMC 7nm or below nodes.

Job Tags

Work alone,

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